Power performance with gated clocks of a pipelined Cordic Core
Cadenas , O. and Megson, G. (2003) Power performance with gated clocks of a pipelined Cordic Core. In: Tang, T. A., Li, W. H. and Yu, H. H. (eds.) 2003 5th International Conference on Asic, Vols 1 and 2, Proceedings. IEEE, New York, pp. 1226-1230. ISBN 078037889X
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This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.