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Compositional technique for synthesising multi-phase regular arrays

Manjunathaiah, M. and Megson, G. (2002) Compositional technique for synthesising multi-phase regular arrays. In: Proceedings of ASAP '02, the 13th IEEE Conference on Application-Specific Systems, Architectures and Processors. IEEE Computer Society, Washington DC, pp. 7-16. ISBN 0769517129

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To link to this item DOI: 10.1109/ASAP.2002.1030700

Abstract/Summary

We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component design into a unified global design. Similarity transformations ar e applied to component designs in the composition stage in order to align data ow between the phases of the computations. Three transformations are considered: rotation, re ection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2-D DCT algorithm which is widely used in many vide ocommunications applications.

Item Type:Book or Report Section
Refereed:Yes
Divisions:Science > School of Mathematical, Physical and Computational Sciences > Department of Computer Science
No Reading authors. Back catalogue items
ID Code:16306
Uncontrolled Keywords:2D DCT algorithm, component designs, compositional technique, computation phases, data flow alignment, hardware component design, high-level design method, high-throughput embedded systems, multi-phase regular array synthesis, reflection transformations, regular array synthesis techniques, rotation transformations, separately evolved component designs, similarity transformations, systolic array synthesis techniques, translation transformations, unified global design, video communications applications
Additional Information:13th IEEE International Conference on Applications-Specific Systems, Architectures and Processors SAN JOSE, CA, JUL 14-19, 2002
Publisher:IEEE Computer Society

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