Parallel pipelined histogram architecturesTools  Cadenas, J., Sherratt, R. S. and Huerta, P. (2011) Parallel pipelined histogram architectures. Electronics Letters, 47 (20). pp. 1118-1120. ISSN 0013-5194 Full text not archived in this repository. To link to this article DOI: 10.1049/el.2011.2390 Abstract/SummaryProposed is a unique cell histogram architecture which will process k data items in parallel to compute 2q histogram bins per time step. An array of m/2q cells computes an m-bin histogram with a speed-up factor of k; k ⩾ 2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.
Related URLs Deposit Details Repository Staff Only: item control page |
Tools
Tools