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Pipelined median architecture

Cadenas Medina, J. (2015) Pipelined median architecture. Electronics Letters, 51 (24). pp. 1999-2001. ISSN 0013-5194

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To link to this item DOI: 10.1049/el.2015.1898

Abstract/Summary

The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared to latest methods in the literature.

Item Type:Article
Refereed:Yes
Divisions:Faculty of Science
ID Code:39965
Uncontrolled Keywords:median, pipeline
Publisher:Institution of Engineering and Technology (IET)

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