Retiming for quick performance of a pipelined IDEA FPGA designCadenas , O. (2004) Retiming for quick performance of a pipelined IDEA FPGA design. In: International Conference on Reconfigurable Computing and FPGAs, Colima, Mexico. Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.
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