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Median architecture by accumulative parallel counters

Cadenas Medina, J., Megson, G. M. and Sherratt, S. ORCID: (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747

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To link to this item DOI: 10.1109/TCSII.2015.2415655


The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

Item Type:Article
Divisions:Life Sciences > School of Biological Sciences > Department of Bio-Engineering
ID Code:36577
Uncontrolled Keywords:Median Filter, Pipelined Processing, Image Processing.


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