Accessibility navigation


Pullpipelining: A technique for systolic pipelined circuits

Cadenas , O. and Megson, G. (2003) Pullpipelining: A technique for systolic pipelined circuits. In: Badawy, W. and Ismail, Y. (eds.) 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, Proceedings. IEEE Computer Soc, pp. 205-210. ISBN 076951944X

Full text not archived in this repository.

Abstract/Summary

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed Control circuits using a synchronous, a semi-synchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.

Item Type:Book or Report Section
Divisions:Faculty of Science > School of Systems Engineering
ID Code:14366
Additional Information:Proceedings Paper 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications JUN 30-JUL 02, 2003 CALGARY, CANADA
Publisher:IEEE Computer Soc

Centaur Editors: Update this record

Page navigation