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Experiences applying OVM 2.0 to an 8B/10B RTL design

Cadenas , O. and Todorovich, E. (2009) Experiences applying OVM 2.0 to an 8B/10B RTL design. In: Roda, V. O., Saito, J. H., Sutter, G. and Boemo, E. (eds.) 2009 5th Southern Conference on Programmable Logic, Proceedings. IEEE, New York, pp. 1-8. ISBN 9781424438464

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To link to this article DOI: 10.1109/SPL.2009.4914897

Abstract/Summary

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

Item Type:Book or Report Section
Refereed:Yes
Divisions:Faculty of Science > School of Systems Engineering
ID Code:14372
Uncontrolled Keywords:formal verification , hardware description languages , object-oriented programming , software portability , software reusability
Additional Information:Proceedings Paper 5th Southern Conference on Programmable Logic APR 01-03, 2009 Sao "Carlos, BRAZIL
Publisher:IEEE

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