Accessibility navigation


Retiming for quick performance of a pipelined IDEA FPGA design

Cadenas , O. (2004) Retiming for quick performance of a pipelined IDEA FPGA design. In: International Conference on Reconfigurable Computing and FPGAs, Colima, Mexico.

Full text not archived in this repository.


Item Type:Conference or Workshop Item (Paper)
Divisions:Faculty of Science > School of Systems Engineering
ID Code:14615

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation