A clocking technique for FPGA pipelined designs
Cadenas , O. and Megson, G. (2004) A clocking technique for FPGA pipelined designs. Journal of Systems Architecture, 50 (11). pp. 687-696. ISSN 1383-7621
Full text not archived in this repository.
To link to this article DOI: 10.1016/j.sysarc.2004.04.001
This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.
Centaur Editors: Update this record