Accessibility navigation


Improving CS-4 user data rate in GPRS enabled devices by using a BLER co-processor

Sherratt, R.S. ORCID: https://orcid.org/0000-0001-7899-4445, Zhang, K.Q. and Wilkes, O.J. (2005) Improving CS-4 user data rate in GPRS enabled devices by using a BLER co-processor. International Journal of Wireless Information Networks, 13 (3). pp. 239-251.

Full text not archived in this repository.

It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.

To link to this item DOI: 10.1007/s10776-005-0013-y

Abstract/Summary

The General Packet Radio Service (GPRS) was developed to allow packet data to be transported efficiently over an existing circuit switched radio network. The main applications for GPRS are in transporting IP datagram’s from the user’s mobile Internet browser to and from the Internet, or in telemetry equipment. A simple Error Detection and Correction (EDC) scheme to improve the GPRS Block Error Rate (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel, improving throughput and the user’s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper.

Item Type:Article
Refereed:Yes
Divisions:Life Sciences > School of Biological Sciences > Department of Bio-Engineering
ID Code:15380
Uncontrolled Keywords:Application data rate - co-processor - FPGA - GPRS - IP transport

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation