Accessibility navigation


Partial dynamic reconfiguration of FPGAs for systolic circuits

Cadenas Medina, O. (2002) Partial dynamic reconfiguration of FPGAs for systolic circuits. PhD thesis, University of Reading

Full text not archived in this repository.


Item Type:Thesis (PhD)
Thesis Supervisor:Megson, G.
Thesis/Report Department:Department of Electronic Engineering
Identification Number/DOI:
Divisions:Faculty of Science
ID Code:18884

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation