Pipelining considerations for an FPGA case
Cadenas, O. and Megson, G. (2001) Pipelining considerations for an FPGA case. In: Euromicro Symposium on Digital Systems Design 2001, 4-6 Sep 2001, Warsaw, Poland, pp. 276-283.
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To link to this item DOI: 10.1109/DSD.2001.952298
This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.