Accessibility navigation


Parallel pipelined array architectures for real-time histogram computation in consumer devices

Cadenas Medina, O., Sherratt, S., Huerta, P. and Kao, W.-C. (2011) Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Transactions on Consumer Electronics, 57 (4). pp. 1460-1464. ISSN 0098-3063

Full text not archived in this repository.

To link to this article DOI: 10.1109/TCE.2011.6131111

Abstract/Summary

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle.

Item Type:Article
Refereed:Yes
Divisions:Faculty of Science > School of Systems Engineering
ID Code:25568
Publisher:IEEE

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation