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Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers

Maden, B. and Guy, C. (1989) Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers. In: IEE European Conference on Circuit Theory and Design, 5-8 September 1989, Brighton, pp. 171-175.

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Abstract/Summary

Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

Item Type:Conference or Workshop Item (Paper)
Refereed:Yes
Divisions:Faculty of Science > School of Systems Engineering
ID Code:27746

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