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Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array

Cadenas Medina, O., Megson, G. M. and Plaks, T. P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: PDPTA'2000: Proceedings of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications. CSREA Press, pp. 3023-3026.

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Item Type:Book or Report Section
Refereed:Yes
Divisions:Faculty of Science > School of Systems Engineering
ID Code:28115
Publisher:CSREA Press

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