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C-slow retimed parallel histogram architectures for consumer imaging devices

Cadenas Medina, J. O., Sherratt, R. S., Huerta, P., Kao, W.-C. and Megson, G. M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics,, 59 (2). pp. 291-295.

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To link to this item DOI: 10.1109/TCE.2013.6531108

Abstract/Summary

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

Item Type:Article
Refereed:Yes
Divisions:Faculty of Life Sciences > School of Biological Sciences > Department of Bio-Engineering
ID Code:33371
Uncontrolled Keywords:Parallel Histograms, Pipelined Array, FPGA, Digital Imaging, Image Processing.

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