Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAsCadenas , O., Brandt, M. A., Megson, G. and Goswami, N. (2004) Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs. In: 2004 IEEE International Symposium on Consumer Electronics, Proceedings. IEEE, New York, pp. 465-469. ISBN 0780385268 Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing. Abstract/SummaryDesign for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).
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