Verification and FPGA circuits of a block-2 fast path-based predictorCadenas , O. and Megson, G. (2006) Verification and FPGA circuits of a block-2 fast path-based predictor. In: Koch, A. and Leong, P. (eds.) 2006 International Conference on Field Programmable Logic and Applications, Proceedings. International Conference on Field Programmable and Logic Applications. IEEE, New York, pp. 213-218. ISBN 9781424403127 Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing. To link to this item DOI: 10.1109/FPL.2006.311216 Abstract/SummaryThis paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.
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