A new organization for a perceptron-based branch predictor and its FPGA implementationCadenas , O., Megson, G. and Jones, D. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, A. and Ranganathan, N. (eds.) IEEE Computer Society Annual Symposium on VLSI, Proceedings - NEW FRONTIERS IN VLSI DESIGN. IEEE Computer Soc, Los Alamitos, pp. 305-306. ISBN 076952365X Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing. Abstract/SummaryAn unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.
Altmetric Deposit Details University Staff: Request a correction | Centaur Editors: Update this record |
Lists
Lists
