FPGA organization for the fast path-based neural branch predictorCadenas , O., Megson, G. and Jones, D. (2005) FPGA organization for the fast path-based neural branch predictor. In: Brebner, G., Chakraborty, S. and Wong, W. F. (eds.) FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings. IEEE, New York, pp. 251-257. ISBN 0780394070 Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing. Abstract/SummaryThis paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.
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