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A clocking technique with power savings in virtex-based pipelined designs

Cadenas, O. and Megson, G. (2002) A clocking technique with power savings in virtex-based pipelined designs. Lecture Notes in Computer Science, 2438. pp. 322-331. ISSN 0302-9743 (special issue 'Field-programmable logic and applications: reconfigurable computing is going mainstream')

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To link to this item DOI: 10.1007/3-540-46117-5_34


This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

Item Type:Article
ID Code:18885

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