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Improving mW/MHz ratio in FPGAs pipelined designs

Cadenas, O. and Megson, G. (2002) Improving mW/MHz ratio in FPGAs pipelined designs. In: Euromicro symposium on digital system design 2002, 4-6 Sep 2002, Dortmund, Germany, pp. 276-282,

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To link to this item DOI: 10.1109/DSD.2002.1115379


This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Item Type:Conference or Workshop Item (Paper)
ID Code:18887
Uncontrolled Keywords:FPGAs pipelined designs, Virtex-based FPGA circuits, clocking technique, logic design, mW/MHz ratio, synchronous functional-equivalent alternative system, systolic design

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