Accessibility navigation

Parallel Architectures for High Speed Multipliers

Maden, B. and Guy, C. (1989) Parallel Architectures for High Speed Multipliers. In: IEEE International Symposium on Circuits and Systems, 1989, 8-11 May 1989, pp. 142-145.

Full text not archived in this repository.

It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.


The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.

Item Type:Conference or Workshop Item (Paper)
ID Code:27748

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation