Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic arrayCadenas Medina, O., Megson, G. M. and Plaks, T. P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: PDPTA'2000: Proceedings of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications. CSREA Press, pp. 3023-3026. Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.
Related URLs Deposit Details University Staff: Request a correction | Centaur Editors: Update this record |
Lists
Lists
