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Parallel pipelined histogram architecture via c-slow retiming

Cadenas Medina, J., Sherratt, S. ORCID:, Huerta, P., Kao, W. C. and Megson, G. M. (2013) Parallel pipelined histogram architecture via c-slow retiming. In: Proceedings of the 2013 IEEE International Conference on Consumer Electronics (ICCE). IEEE, pp. 230-231. ISBN 9781467313612

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To link to this item DOI: 10.1109/ICCE.2013.6486871


A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

Item Type:Book or Report Section
Divisions:Life Sciences > School of Biological Sciences > Department of Bio-Engineering
ID Code:32267
Additional Information:Paper originally presented at IEEE International Conference on Consumer Electronics, Las Vegas, USA, Jan 2013


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