A parallel quantum histogram architecture

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Megson, G.M., Cadenas, J.O., Sherratt, R.S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P. and Kao, W.C. (2013) A parallel quantum histogram architecture. IEEE Transactions on Circuits and Systems II, Express Briefs, 60 (7). pp. 437-441. ISSN 1549-7747

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To link to this item DOI: 10.1109/TCSII.2013.2258263

Abstract/Summary

A parallel formulation of an algorithm for the histogram computation of n data items using an on-the-fly data decomposition and a novel quantum-like representation (QR) is developed. The QR transformation separates multiple data read operations from multiple bin update operations thereby making it easier to bind data items into their corresponding histogram bins. Under this model the steps required to compute the histogram is n/s + t steps, where s is a speedup factor and t is associated with pipeline latency. Here, we show that an overall speedup factor, s, is available for up to an eightfold acceleration. Our evaluation also shows that each one of these cells requires less area/time complexity compared to similar proposals found in the literature.

Item Type:	Article
Refereed:	Yes
Divisions:	Life Sciences > School of Biological Sciences > Department of Bio-Engineering
ID Code:	32296
Uncontrolled Keywords:	Histogram, parallel architectures, parallel algorithms, quantum representation.
Publisher:	IEEE

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[1] W. C. Kao, S. H. Wang, L. Y. Chen, Y. Lin, “Design considerations of color image processing pipeline for digital cameras,” IEEE Trans, Consumer Electron. 52 (2006) 1144-1152 [2] C. T. Chiu, et. al., “Real-time tone-mapping processor with integrated photographic and gradient compression using 0.13um technology on an ARM SoC platform,” J. on Signal Proc. Syst. 64 (2011) 93-107. [3] J. Cadenas, R.S. Sherratt, P. Huerta, “Parallel pipelined histogram architectures,” Elecron. Lett. 47 (2011) 1118-1120. [4] J. O. Cadenas, R. S. Sherratt, P. Huerta, W. C. Kao, “Parallel pipelined array architectures for real-time histogram computation in consumer devices,” IEEE Trans. Consumer Electron. 57 (2011) 1460-1464. [5] C. Leiserson, F. Rose, J. Saxe, “Optimizing synchronous circuits by retiming,” 3rd Caltech Conf. on VLSI, 1 (1993). [6] M. A. Neilsen and I. L. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, Cambridge, 2000. [7] U. Banerjee, “An introduction to a formal theory of dependence analysis, Springer,” The J. of Supercomputing, 2 (1988), 133-149. [8] S. Muchnick, Advanced Compiler Design Implementation, Academic Press, London, 1997. [9] T. Cormen, C. Leiserson, R. Rivest and C. Stein, Introduction to Algorithms, 2nd Ed. The MIT Press, Cambridge, 2003. [10] J. F. Wakerly, Digital Design Principles and Practice, 4th ed., Pearson Prentice Hall, New Jersey, 2006 [11] S. Muller, “A new programmable VLSI architecture for histogram and statistics computation in different windows,” Proc. Int. Conf. on Image Processing, DC, USA, (1995), pp. 73-76. [12] E. Garcia, “Implementing a histogram for image processing applications,” Xcell Journal Online 38, Xilinx (2000), pp. 46-47. [13] B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs, Oxford University Press, New York, 2000. [14] H.T Kung, L. M. Ruane, D. W. L. Yen, “Two-level pipelined systolic array for multidimensional convolution,” Image and Vision Compu. 1 (1983) 30-36. [15] Q. Gan, J. M. P. Langlois, Y. Savaria, “Parallel array histogram architecture for embedded implementation,” Elecron. Lett. 49 (2013) 99-101.

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A parallel quantum histogram architecture

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