Accessibility navigation

Pipelined median architecture

Cadenas Medina, J. (2015) Pipelined median architecture. Electronics Letters, 51 (24). pp. 1999-2001. ISSN 0013-5194

Text - Accepted Version
· Please see our End User Agreement before downloading.


It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.

To link to this item DOI: 10.1049/el.2015.1898


The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared to latest methods in the literature.

Item Type:Article
ID Code:39965
Uncontrolled Keywords:median, pipeline
Publisher:Institution of Engineering and Technology (IET)


Downloads per month over past year

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation