Generic construction of monitors for floating point unit designsGoni, O., Todorovich, E. and Cadenas, O. (2012) Generic construction of monitors for floating point unit designs. In: 8th Southern Conference on Programmable Logic. Southern Conference on Programmable Logic. IEEE, Bento Goncalves, Brazil, pp. 213-220. ISBN 9781467301862 Full text not archived in this repository. It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing. To link to this item DOI: 10.1109/SPL.2012.6211776 Abstract/SummaryThis paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.
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