Accessibility navigation

Efficient operator pipelining in a bit serial genetic algorithm engine

Bland, I. M. and Megson, G. (1997) Efficient operator pipelining in a bit serial genetic algorithm engine. Electronics Letters, 33 (12). pp. 1026-1028. ISSN 0013-5194

Text (no figures included) - Accepted Version
· Please see our End User Agreement before downloading.


It is advisable to refer to the publisher's version if you intend to cite from this work. See Guidance on citing.


The authors propose a bit serial pipeline used to perform the genetic operators in a hardware genetic algorithm. The bit-serial nature of the dataflow allows the operators to be pipelined, resulting in an architecture which is area efficient, easily scaled and is independent of the lengths of the chromosomes. An FPGA implementation of the device achieves a throughput of >25 million genes per second

Item Type:Article
ID Code:4636
Uncontrolled Keywords:genetic algorithms, systolic arrays, bit serial
Publisher:Institution of Engineering and Technology (IET)
Publisher Statement:This paper is a postprint of a paper submitted to and accepted for publication in Electronic Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library


Downloads per month over past year

University Staff: Request a correction | Centaur Editors: Update this record

Page navigation