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Systolic random number generation for genetic algorithms

Bland, I. M. and Megson, G. M. (1996) Systolic random number generation for genetic algorithms. Electronics Letters, 32 (12). pp. 1069-1070. ISSN 0013-5194

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To link to this item DOI: 10.1049/el:19960709


A parallel hardware random number generator for use with a VLSI genetic algorithm processing device is proposed. The design uses an systolic array of mixed congruential random number generators. The generators are constantly reseeded with the outputs of the proceeding generators to avoid significant biasing of the randomness of the array which would result in longer times for the algorithm to converge to a solution. 1 Introduction In recent years there has been a growing interest in developing hardware genetic algorithm devices [1, 2, 3]. A genetic algorithm (GA) is a stochastic search and optimization technique which attempts to capture the power of natural selection by evolving a population of candidate solutions by a process of selection and reproduction [4]. In keeping with the evolutionary analogy, the solutions are called chromosomes with each chromosome containing a number of genes. Chromosomes are commonly simple binary strings, the bits being the genes.

Item Type:Article
ID Code:7450
Uncontrolled Keywords:VLSI, genetic algorithms, random number generation systolic array, VLSI processing device, genetic algorithm, parallel hardware, random number generator
Publisher:Institution of Engineering and Technology (IET)

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