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Items where Author is "Cadenas Medina, Dr Jose"

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Megson, G.M., Cadenas , J.O., Sherratt, R.S., Huerta, P. and Kao, W.C. (2013) A parallel quantum histogram architecture. IEEE Transactions on Circuits and Systems II, Express Briefs, 60 (7). pp. 437-441. ISSN 1549-7747 doi: 10.1109/TCSII.2013.2258263

Cadenas Medina, J. O., Sherratt, R. S., Huerta, P., Kao, W.-C. and Megson, G. M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics,, 59 (2). pp. 291-295. doi: 10.1109/TCE.2013.6531108

Cadenas Medina, J., Sherratt, S., Huerta, P., Kao, W. C. and Megson, G. M. (2013) Parallel pipelined histogram architecture via c-slow retiming. In: Proceedings of the 2013 IEEE International Conference on Consumer Electronics (ICCE). IEEE, pp. 230-231. ISBN 9781467313612 doi: 10.1109/ICCE.2013.6486871

Cadenas Medina, O., Megson, G.M., Sherratt, S. and Huerta, P. (2012) Fast median calculation method. Electronic Letters, 48 (10). pp. 558-560. ISSN 0013-5194 doi: 10.1049/el.2012.0343

Mitchell, R., Harwin, W., Cadenas Medina, O., Guy, C., Gong, A., Potter, B. and Warwick, K., eds. (2012) Cybernetics, Circuits and Computing. Pearson, Harlow, pp499. ISBN 9781780160672

Cadenas Medina, O., Sherratt, S., Huerta, P. and Kao, W.-C. (2011) Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Transactions on Consumer Electronics, 57 (4). pp. 1460-1464. ISSN 0098-3063 doi: 10.1109/TCE.2011.6131111

Cadenas, J., Sherratt, R. S. and Huerta, P. (2011) Parallel pipelined histogram architectures. Electronics Letters, 47 (20). pp. 1118-1120. ISSN 0013-5194 doi: 10.1049/el.2011.2390

Sherratt, R. S. and Cadenas, O. (2010) A double data rate (DDR) architecture for OFDM based wireless consumer devices. IEEE Transactions on Consumer Electronics, 56 (1). pp. 23-26. ISSN 0098-3063 doi: 10.1109/TCE.2010.5439121

Sherratt, R. S. and Cadenas, O. (2010) A double data rate (DDR) architecture for OFDM based wireless consumer devices. In: IEEE International Conference on Consumer Electronics, Jan 2010, Las Vegas, USA.

The University of Reading (2009) Dual carrier modulation soft demapper. US 2009/0304094 A1. doi: US 2009/0304094 A1

Cadenas , O. and Todorovich, E. (2009) Experiences applying OVM 2.0 to an 8B/10B RTL design. In: Roda, V. O., Saito, J. H., Sutter, G. and Boemo, E. (eds.) 2009 5th Southern Conference on Programmable Logic, Proceedings. IEEE, New York, pp. 1-8. ISBN 9781424438464 doi: 10.1109/SPL.2009.4914897

The University of Reading, and Oswaldo Cadenas (2008) Processing system accepting exceptional numbers. PCT/GB2007/004956. doi: PCT/GB2007/004956

Sherratt, R.S., Khan, J.R. and Cadenas , O. (2008) A Packet/Frame sync detector based on statistical mode with application to wireless-USB. In: IEEE International Symposium on Consumer Electronics (ISCE 2008), Portugal. doi: 10.1109/ISCE.2008.4559528

Molina, A. and Cadenas , O. (2007) Functional verification: approaches and challenges. Latin American Applied Research, 37 (1). pp. 65-69. ISSN 0327-0793

Yang, R., Sherratt, R.S. and Cadenas, O. (2007) FPGA based dual carrier modulation soft mapper and demapper for the MB-OFDM UWB platform. In: EPSRC 8th Annual Postgraduate Symposium on the Convergence of Telecommunications, Networking and Broadcasting (PGNET 2007),, Liverpool, UK.

Sherratt, R. S., Cadenas , O. and Yang, R. F. (2007) A practical low cost architecture for a MB-OFDM equalizer (ECMA-368). In: 2007 IEEE International Symposium on Consumer Electronics, Vols 1 and 2. IEEE International Symposium on Consumer Electronics. IEEE, pp. 668-671. ISBN 781424411092 doi: 10.1109/ISCE.2007.4382235

Cadenas , O. and Megson, G. (2006) Verification and FPGA circuits of a block-2 fast path-based predictor. In: Koch, A. and Leong, P. (eds.) 2006 International Conference on Field Programmable Logic and Applications, Proceedings. International Conference on Field Programmable and Logic Applications. IEEE, New York, pp. 213-218. ISBN 9781424403127 doi: 10.1109/FPL.2006.311216

Cadenas , O., Megson, G. and Jones, D. (2005) FPGA organization for the fast path-based neural branch predictor. In: Brebner, G., Chakraborty, S. and Wong, W. F. (eds.) FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings. IEEE, New York, pp. 251-257. ISBN 0780394070

Cadenas , O., Megson, G. and Jones, D. (2005) Implementation of a block based neural branch predictor. In: Proceedings 8th Euromicro Conference on Digital System Design, Porto, Portugal.

Sherratt, R. S., Cadenas , O., Goswami, N. and Makino, S. (2005) An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers. In: Bradbeer, R. S. and Shum, Y. H. (eds.) Proceedings of the Ninth International Symposium on Consumer Electronics 2005. IEEE International Symposium on Consumer Electronics. IEEE, New York, pp. 209-214. ISBN 0780389204

Sherratt, R. S., Cadenas , O. and Goswami, N. (2005) A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers. IEEE Transactions on Consumer Electronics, 51 (3). pp. 798-802. ISSN 0098-3063

Cadenas , O., Megson, G. and Jones, D. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, A. and Ranganathan, N. (eds.) IEEE Computer Society Annual Symposium on VLSI, Proceedings - NEW FRONTIERS IN VLSI DESIGN. IEEE Computer Soc, Los Alamitos, pp. 305-306. ISBN 076952365X

Cadenas , O. and Megson, G. M. (2004) A FPGA Pipelined Backward Adaptive Scalar Quantizer. In: IASTED International Conference on Circuits, Signals and Systems 2004, Clearwater, Florida, USA.

Cadenas, O. and Megson, G. M. (2004) Fractal quantization. In: 2004 IEEE International Symposium on Consumer Electronics, Proceedings. IEEE, New York, pp. 461-464. ISBN 0780385268

Cadenas , O., Brandt, M. A., Megson, G. and Goswami, N. (2004) Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs. In: 2004 IEEE International Symposium on Consumer Electronics, Proceedings. IEEE, New York, pp. 465-469. ISBN 0780385268

Cadenas , O. (2004) Retiming for quick performance of a pipelined IDEA FPGA design. In: International Conference on Reconfigurable Computing and FPGAs, Colima, Mexico.

Cadenas , O. and Megson, G. (2004) A clocking technique for FPGA pipelined designs. Journal of Systems Architecture, 50 (11). pp. 687-696. ISSN 1383-7621 doi: 10.1016/j.sysarc.2004.04.001

Plaks, T. P., Megson, G. M., Cadenas Medina, J. O. and Alexandrov, V. N. (2003) A linear algebra processor using Monte Carlo methods. In: 2003 MAPLD International Conference, 9-11 September 2003, Washington DC, USA.

Cadenas , O., Megson, G.M. and Plaks, T. (2003) FPGA circuits for a Monte-Carlo based matrix inversion. In: The 2003 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA.

Cadenas , O. and Megson, G. (2003) Power performance with gated clocks of a pipelined Cordic Core. In: Tang, T. A., Li, W. H. and Yu, H. H. (eds.) 2003 5th International Conference on Asic, Vols 1 and 2, Proceedings. IEEE, New York, pp. 1226-1230. ISBN 078037889X

Cadenas , O. and Megson, G. (2003) Pullpipelining: A technique for systolic pipelined circuits. In: Badawy, W. and Ismail, Y. (eds.) 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, Proceedings. IEEE Computer Soc, pp. 205-210. ISBN 076951944X

Cadenas Medina, O. and Megson, G.M. (2003) An average-case classifier algorithm and FPGA implementation. In: Iasted Circuits, Signals and Systems, Cancun, Mexico.

Cadenas, O. and Megson, G. (2002) Improving mW/MHz ratio in FPGAs pipelined designs. In: Euromicro symposium on digital system design 2002, 4-6 Sep 2002, Dortmund, Germany, pp. 276-282. doi: 10.1109/DSD.2002.1115379

Cadenas Medina, O. (2002) Partial dynamic reconfiguration of FPGAs for systolic circuits. PhD thesis, University of Reading.

Cadenas, O. and Megson, G. (2002) A clocking technique with power savings in virtex-based pipelined designs. Lecture Notes in Computer Science, 2438. pp. 322-331. ISSN 0302-9743 doi: 10.1007/3-540-46117-5_34 (special issue 'Field-programmable logic and applications: reconfigurable computing is going mainstream')

Cadenas, O. and Megson, G. (2001) Pipelining considerations for an FPGA case. In: Euromicro Symposium on Digital Systems Design 2001, 4-6 Sep 2001, Warsaw, Poland, pp. 276-283. doi: 10.1109/DSD.2001.952298

Cadenas, O. and Megson, G. (2001) A n-Bit Reconfigurable Scalar Quantiser. Lecture Notes in Computer Science, 2147. pp. 420-429. ISSN 1611-3349 doi: 10.1007/3-540-44687-7_43

Cadenas Medina, O., Megson, G. M. and Plaks, T. P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: PDPTA'2000: Proceedings of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications. CSREA Press, pp. 3023-3026.

Cadenas, J. O., Megson, G. M. and Plaks, T. P. (2000) Quantitative evaluation of three reconfiguration strategies on FPGAs: a case study. In: International Conference on High Performance Computing in Asia-Pacific Region, 14-17 May 2000, Beijing, China, pp. 337-342. doi: 10.1109/HPC.2000.846574

Plaks, T. P., Cadenas Medina, J. O. and Megson, G. M. (1999) Experiences using reconfigurable FPGAs in implementing Monte-Carlo methods. In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1999. CSREA Press, pp. 1131-1137. ISBN 1892512157

This list was generated on Sun Jul 27 22:56:55 2014 BST.

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