Laszuk, D., Cadenas, O. and Nasuto, S. J. (2016) EMD performance comparison: single vs double floating points. International journal of signal processing systems, 4 (4). pp. 349-353. ISSN 2315-4535

Cadenas, J. O., Megson, G. M. and Luengo Hendriks, C. L. (2016) Preconditioning 2D integer data for fast convex hull computations. PLoS ONE, 11 (3). e0149860. ISSN 1932-6203 doi: https://doi.org/10.1371/journal.pone.0149860

Cadenas Medina, J. (2015) Pipelined median architecture. Electronics Letters, 51 (24). pp. 1999-2001. ISSN 0013-5194 doi: https://doi.org/10.1049/el.2015.1898

Cadenas, J. O., Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445, Howlett, D., Guy, C. and Lundqvist, K. (2015) Virtualization for cost-effective teaching of assembly language programming. IEEE Transactions on Education, 58 (4). pp. 282-288. ISSN 0018-9359 doi: https://doi.org/10.1109/TE.2015.2405895

Cadenas Medina, J., Megson, G. M. and Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445 (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747 doi: https://doi.org/10.1109/TCSII.2015.2415655

Laszuk, D., Cadenas, O. and Nasuto, S. J. (2015) Objective Empirical Mode Decomposition metric. In: 38th International Conference on Telecommunications and Signal Processing (TSP). IEEE, pp. 504-507. ISBN 9781479984985 doi: https://doi.org/10.1109/TSP.2015.7296314

Odeh, M., Warwick, K. and Cadenas Medina, J. (2014) Major differences of cloud computing adoption in universities: Europe vs. Middle East. Journal of Emerging Trends in Computing and Information Sciences, 5 (12). pp. 948-952. ISSN 2079-8407

Cadenas Medina, J. and Megson, G. M. (2014) Rapid preconditioning of data for accelerating convex hull algorithms. Electronics Letters, 50 (4). pp. 270-272. ISSN 0013-5194 doi: https://doi.org/10.1049/el.2013.3507

Ye, Y., Cadenas Medina, J. and Megson, G. (2014) Acceleration and visualization of Dynamic Network Optimization. In: International Conference on Computing, Networking and Communications (ICNC), 3-6 Feb. 2014, Honolulu, HI, pp. 726-730.

Megson, G.M., Cadenas, J.O., Sherratt, R.S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P. and Kao, W.C. (2013) A parallel quantum histogram architecture. IEEE Transactions on Circuits and Systems II, Express Briefs, 60 (7). pp. 437-441. ISSN 1549-7747 doi: https://doi.org/10.1109/TCSII.2013.2258263

Cadenas Medina, J. O., Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P., Kao, W.-C. and Megson, G. M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics,, 59 (2). pp. 291-295. doi: https://doi.org/10.1109/TCE.2013.6531108

Cadenas Medina, J., Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P., Kao, W. C. and Megson, G. M. (2013) Parallel pipelined histogram architecture via c-slow retiming. In: Proceedings of the 2013 IEEE International Conference on Consumer Electronics (ICCE). IEEE, pp. 230-231. ISBN 9781467313612 doi: https://doi.org/10.1109/ICCE.2013.6486871

Ye, Y., Megson, G. and Cadenas Medina, J. (2013) Asynchronous distributed parallelization of mobile network optimization algorithms. In: 3rd International Conference on Wireless Communications, Vehicular Technology, Information Theory and Aerospace & Electronic Systems (VITAE), 2013, 24-27 June 2013, Atlantic City, NJ, pp. 1-6.

Curi-Quintal, L. F., Cadenas Medina, J. and Megson, G. M. (2013) Bit-index sort: a fast non-comparison integer sorting algorithm for permutations. In: International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), 2013, 9-11 May 2013, Konya, pp. 83-87.

Ye, Y., Cadenas Medina, J. and Megson, G. (2013) Distributed parallelization of greedy Mobile Network Optimization algorithms. In: 21st International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2013, 18-20 Sept. 2013, Primosten, pp. 1-5.

Curi-Quintal, L. and Cadenas Medina, J. (2013) Software-based study of a non-sorting method for median calculation on a set of integer numbers. In: 12th WSEAS Int. Conf. on Signal processing, Robotics and Automation, Feb 2013, Cambridge.

Cadenas Medina, O., Megson, G. M., Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445 and Huerta, P. (2012) Fast median calculation method. Electronics Letters, 48 (10). pp. 558-560. ISSN 0013-5194 doi: https://doi.org/10.1049/el.2012.0343

Goni, O., Todorovich, E. and Cadenas, O. (2012) Generic construction of monitors for floating point unit designs. In: 8th Southern Conference on Programmable Logic. Southern Conference on Programmable Logic. IEEE, Bento Goncalves, Brazil, pp. 213-220. ISBN 9781467301862 doi: https://doi.org/10.1109/SPL.2012.6211776

Mitchell, R., Harwin, W. ORCID: https://orcid.org/0000-0002-3928-3381, Cadenas Medina, O., Guy, C., Gong, A., Potter, B. and Warwick, K., eds. (2012) Cybernetics, Circuits and Computing. Pearson, Harlow, pp499. ISBN 9781780160672

Curi-Quintal, L. and Cadenas, O. (2012) A parallel formulation for the simulation of a generic branch predictor. In: International Conference on Parallel and Distributed Processing Techniques and Applications, July 2012, Las Vegas,, pp. 977-981.

Cadenas Medina, O., Sherratt, S. ORCID: https://orcid.org/0000-0001-7899-4445, Huerta, P. and Kao, W.-C. (2011) Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Transactions on Consumer Electronics, 57 (4). pp. 1460-1464. ISSN 0098-3063 doi: https://doi.org/10.1109/TCE.2011.6131111

Cadenas, J., Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445 and Huerta, P. (2011) Parallel pipelined histogram architectures. Electronics Letters, 47 (20). pp. 1118-1120. ISSN 0013-5194 doi: https://doi.org/10.1049/el.2011.2390

Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445 and Cadenas, O. (2010) A double data rate (DDR) architecture for OFDM based wireless consumer devices. IEEE Transactions on Consumer Electronics, 56 (1). pp. 23-26. ISSN 0098-3063 doi: https://doi.org/10.1109/TCE.2010.5439121

Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445 and Cadenas, O. (2010) A double data rate (DDR) architecture for OFDM based wireless consumer devices. In: IEEE International Conference on Consumer Electronics, Jan 2010, Las Vegas, USA.

The University of Reading (2009) Dual carrier modulation soft demapper. US 2009/0304094 A1. doi: US 2009/0304094 A1

Cadenas , O. and Todorovich, E. (2009) Experiences applying OVM 2.0 to an 8B/10B RTL design. In: Roda, V. O., Saito, J. H., Sutter, G. and Boemo, E. (eds.) 2009 5th Southern Conference on Programmable Logic, Proceedings. IEEE, New York, pp. 1-8. ISBN 9781424438464 doi: https://doi.org/10.1109/SPL.2009.4914897

The University of Reading, and Oswaldo Cadenas (2008) Processing system accepting exceptional numbers. PCT/GB2007/004956. doi: PCT/GB2007/004956

Sherratt, R.S. ORCID: https://orcid.org/0000-0001-7899-4445, Khan, J.R. and Cadenas , O. (2008) A Packet/Frame sync detector based on statistical mode with application to wireless-USB. In: IEEE International Symposium on Consumer Electronics (ISCE 2008), Portugal. doi: https://doi.org/10.1109/ISCE.2008.4559528

Todorovich, E. and Cadenas Medina, J. (2007) TCL/TK for EDA tools. In: Southern Conference on Programmable Logic. IEEE, Mr del Plata, Argentina, pp. 107-112. ISBN 1-4244-0606-4 doi: https://doi.org/10.1109/SPL.2007.371732

Molina, A. and Cadenas , O. (2007) Functional verification: approaches and challenges. Latin American Applied Research, 37 (1). pp. 65-69. ISSN 0327-0793

Yang, R., Sherratt, R.S. ORCID: https://orcid.org/0000-0001-7899-4445 and Cadenas, O. (2007) FPGA based dual carrier modulation soft mapper and demapper for the MB-OFDM UWB platform. In: EPSRC 8th Annual Postgraduate Symposium on the Convergence of Telecommunications, Networking and Broadcasting (PGNET 2007),, Liverpool, UK.

Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445, Cadenas , O. and Yang, R. F. (2007) A practical low cost architecture for a MB-OFDM equalizer (ECMA-368). In: 2007 IEEE International Symposium on Consumer Electronics, Vols 1 and 2. IEEE International Symposium on Consumer Electronics. IEEE, pp. 668-671. ISBN 781424411092 doi: https://doi.org/10.1109/ISCE.2007.4382235

Cadenas , O. and Megson, G. (2006) Verification and FPGA circuits of a block-2 fast path-based predictor. In: Koch, A. and Leong, P. (eds.) 2006 International Conference on Field Programmable Logic and Applications, Proceedings. International Conference on Field Programmable and Logic Applications. IEEE, New York, pp. 213-218. ISBN 9781424403127 doi: https://doi.org/10.1109/FPL.2006.311216

Cadenas , O., Megson, G. and Jones, D. (2005) FPGA organization for the fast path-based neural branch predictor. In: Brebner, G., Chakraborty, S. and Wong, W. F. (eds.) FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings. IEEE, New York, pp. 251-257. ISBN 0780394070

Cadenas , O., Megson, G. and Jones, D. (2005) Implementation of a block based neural branch predictor. In: Proceedings 8th Euromicro Conference on Digital System Design, Porto, Portugal.

Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445, Cadenas , O., Goswami, N. and Makino, S. (2005) An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers. In: Bradbeer, R. S. and Shum, Y. H. (eds.) Proceedings of the Ninth International Symposium on Consumer Electronics 2005. IEEE International Symposium on Consumer Electronics. IEEE, New York, pp. 209-214. ISBN 0780389204

Sherratt, R. S. ORCID: https://orcid.org/0000-0001-7899-4445, Cadenas , O. and Goswami, N. (2005) A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers. IEEE Transactions on Consumer Electronics, 51 (3). pp. 798-802. ISSN 0098-3063

Cadenas , O., Megson, G. and Jones, D. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, A. and Ranganathan, N. (eds.) IEEE Computer Society Annual Symposium on VLSI, Proceedings - NEW FRONTIERS IN VLSI DESIGN. IEEE Computer Soc, Los Alamitos, pp. 305-306. ISBN 076952365X

Cadenas , O. and Megson, G. M. (2004) A FPGA Pipelined Backward Adaptive Scalar Quantizer. In: IASTED International Conference on Circuits, Signals and Systems 2004, Clearwater, Florida, USA.

Cadenas, O. and Megson, G. M. (2004) Fractal quantization. In: 2004 IEEE International Symposium on Consumer Electronics, Proceedings. IEEE, New York, pp. 461-464. ISBN 0780385268

Cadenas , O., Brandt, M. A., Megson, G. and Goswami, N. (2004) Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs. In: 2004 IEEE International Symposium on Consumer Electronics, Proceedings. IEEE, New York, pp. 465-469. ISBN 0780385268

Cadenas , O. (2004) Retiming for quick performance of a pipelined IDEA FPGA design. In: International Conference on Reconfigurable Computing and FPGAs, Colima, Mexico.

Cadenas , O. and Megson, G. (2004) A clocking technique for FPGA pipelined designs. Journal of Systems Architecture, 50 (11). pp. 687-696. ISSN 1383-7621 doi: https://doi.org/10.1016/j.sysarc.2004.04.001

Plaks, T. P., Megson, G. M., Cadenas Medina, J. O. and Alexandrov, V. N. (2003) A linear algebra processor using Monte Carlo methods. In: 2003 MAPLD International Conference, 9-11 September 2003, Washington DC, USA.

Cadenas , O., Megson, G.M. and Plaks, T. (2003) FPGA circuits for a Monte-Carlo based matrix inversion. In: The 2003 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA.

Cadenas , O. and Megson, G. (2003) Power performance with gated clocks of a pipelined Cordic Core. In: Tang, T. A., Li, W. H. and Yu, H. H. (eds.) 2003 5th International Conference on Asic, Vols 1 and 2, Proceedings. IEEE, New York, pp. 1226-1230. ISBN 078037889X

Cadenas , O. and Megson, G. (2003) Pullpipelining: A technique for systolic pipelined circuits. In: Badawy, W. and Ismail, Y. (eds.) 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, Proceedings. IEEE Computer Soc, pp. 205-210. ISBN 076951944X

Cadenas Medina, O. and Megson, G.M. (2003) An average-case classifier algorithm and FPGA implementation. In: Iasted Circuits, Signals and Systems, Cancun, Mexico.

Cadenas, O. and Megson, G. (2002) Improving mW/MHz ratio in FPGAs pipelined designs. In: Euromicro symposium on digital system design 2002, 4-6 Sep 2002, Dortmund, Germany, pp. 276-282. doi: https://doi.org/10.1109/DSD.2002.1115379

Cadenas Medina, O. (2002) Partial dynamic reconfiguration of FPGAs for systolic circuits. PhD thesis, University of Reading.

Cadenas, O. and Megson, G. (2002) A clocking technique with power savings in virtex-based pipelined designs. Lecture Notes in Computer Science, 2438. pp. 322-331. ISSN 0302-9743 doi: https://doi.org/10.1007/3-540-46117-5_34 (special issue 'Field-programmable logic and applications: reconfigurable computing is going mainstream')

Cadenas, O. and Megson, G. (2001) Pipelining considerations for an FPGA case. In: Euromicro Symposium on Digital Systems Design 2001, 4-6 Sep 2001, Warsaw, Poland, pp. 276-283. doi: https://doi.org/10.1109/DSD.2001.952298

Cadenas, O. and Megson, G. (2001) A n-Bit Reconfigurable Scalar Quantiser. Lecture Notes in Computer Science, 2147. pp. 420-429. ISSN 1611-3349 doi: https://doi.org/10.1007/3-540-44687-7_43

Cadenas Medina, O., Megson, G. M. and Plaks, T. P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: PDPTA'2000: Proceedings of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications. CSREA Press, pp. 3023-3026.

Cadenas, J. O., Megson, G. M. and Plaks, T. P. (2000) Quantitative evaluation of three reconfiguration strategies on FPGAs: a case study. In: International Conference on High Performance Computing in Asia-Pacific Region, 14-17 May 2000, Beijing, China, pp. 337-342. doi: https://doi.org/10.1109/HPC.2000.846574

Plaks, T. P., Cadenas Medina, J. O. and Megson, G. M. (1999) Experiences using reconfigurable FPGAs in implementing Monte-Carlo methods. In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1999. CSREA Press, pp. 1131-1137. ISBN 1892512157